1. Field of the Invention
The present invention relates generally to semiconductor fabrication methods and, more particularly, to fabrication of interconnect structures, e.g., vias, in semiconductor devices containing, for instance, copper.
2. Description of Related Art
Vias are formed in semiconductor structures to connect components on one layer to components on another. During manufacturing processes various imperfections may manifest themselves in an integrated circuit wafer. In order to reduce the effects that may be currently associated with such imperfections, as well as future effects which may develop, wafer tests are performed for predetermined parameters to help assure operation. For instance, process and material weaknesses may be identified by applying a set of stress tests during or at the conclusion of chip fabrication.
Stress testing can help to control the incidence of early-life failure or so-called infant mortality in a semiconductor product, such as in the case where effects of moderate or long term operation of a product may be simulated. A simulation may be enacted by relatively short-term application of expected or augmented stresses during a reliability-testing phase, thereby inducing failures in marginal components. A particular implementation of the concept, known as high temperature or stress-migration baking, applies stress in the form of radiant energy to generate testing-reliability information for a given integrated circuit(s) or component(s). The high temperatures, typically on the order of 150° C. to 250° C., may expose defects that could cause suboptimal performance or even failure when a product is later distributed and placed into use.
According to certain scenarios, such as those involving the coupling of an interconnect structure (e.g., via) to an electrically conductive layer (e.g., copper), slight or hidden imperfections corresponding to grains in the electrically conductive layer may produce failure issues that develop or become evident later or during stress-migration baking. That is, performance tests conducted prior to application of the stress-migration baking may expose no or relatively few failure incidents in this regard. A consequence of the stress-migration baking step is to cause migration of micro-vacancies in the electrically conductive layer and movement toward/clustering of those micro-vacancies to a vicinity under the interconnect structure, thereby creating void(s) between the interconnect structure and the electrically conductive layer. Such voids (i.e., vacancy clusters) can introduce resistance to the interconnect structure or, in more pronounced cases, cause the conductive pathway of a via to be blinded, obstructed or otherwise inhibited with a commensurately detrimental effect upon manufacturing reliability, efficiency and cost.
A related issue in semiconductor manufacturing involving, for instance, a copper process, is adhesion between a barrier layer in an interconnect structure, such as a via, and the underlying electrically conductive structure, e.g., in this case, the copper. Failure to achieve good adhesion may undesirably increase via resistance.
Yet another issue presented at the juncture between the interconnect structure (e.g., via) and electrically conductive layer (e.g., copper) is the physical stress gradient that naturally exists at this interface during processing and reliability testing.
A need thus exists in the prior art for an interconnect structure that is not unduly susceptible to the effects of vacancy clustering. A further need exists for a method of assuring good via barrier/copper adhesion and/or reducing the mentioned physical stress gradient.